1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a load resistor for a static random access memory (SRAM).
2. Description of the Related Art
A SRAM is widely used in integrated circuits, and plays an especially important role in the electronic industry. The unanimous target for the industries is to fabricate a device with reduced dimensions and high quality. A load resistor is one of the devices that constitute a SRAM cell and is usually made of lightly doped or undoped polysilicon.
A circuit diagram of a SRAM cell is shown in FIG. 1. The SRAM cell includes two load resistors, R.sub.1, and R.sub.2, two pull down transistors, Q.sub.1 and Q.sub.2, and two pass transistors, Q.sub.3 and Q.sub.4. A first polysilicon layer is employed as a gate of the transistor Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4, and a second polysilicon is formed as load resistor. The second polysilicon layer comprises a highly resistant part used as a load resistor, and a minorly resistant part used as an interconnect. In the prior technique, the low resistant part, that is, the interconnect, is formed by heavily doping a part of the second polysilicon layer, while the high resistant part, that is, the load resistor, is formed by lightly doping the second polysilicon layer. The interconnect and the load resistor construct a circuit path from the power source V.sub.CC to the nodes A and B.
FIGS. 2A-2D are schematic, cross-sectional views illustrating fabrication of an SRAM. Referring to FIG. 2A, a substrate 200 has at least an isolation structure 202, a buried contact 204 and a defined polysilicon layer 206 formed thereon. An inter-poly dielectric (IPD) layer 208 is formed over the substrate 200.
The IPD layer 208 is patterned and then etched to remove a portion of the IPD layer 208 and to expose the polysilicon layer 206, as shown in FIG. 2B. A polysilicon layer 210 is formed on the substrate 200 and is doped with impurities by ion implantation 212. The dosage of the ion implantation 212 is decided by the resistivity of a load resistor in a subsequent process. The polysilicon layer 210 is then defined to form a desired pattern for an interconnect and the load resistor.
An ion implantation mask 214 is then formed on the defined polysilicon layer 210 to cover a pre-determined position for the poly load 210b, as shown in FIG. 2C. An ion implantation 216 is performed on the polysilicon layer 210a exposed by the ion implantation mask 214. The polysilicon layer 210a with ion implantation 216 serves as a part of the interconnect and the polysilicon 210b covered by the ion implantation mask 214 is used as a load resistor. The polysilicon layer 210a should be doped with a high enough dosage by the ion implantation 216, to thereby serve as the interconnect. An annealing step is performed on the polysilicon layer 210a, 210b to activate the ions inside.
Referring to FIG. 2D, an inter-layer dielectric (ILD) layer 218 is formed over the substrate 200 and a contact 220 is formed within the ILD layer 218 and the IPD layer 208a. A wiring line 222 is then formed on the ILD layer 218 and is electrically connected with the substrate 200 through the contact 220.
As mentioned above, the processes for the load resistor 210b at least includes the steps of deposition, ion implantation, annealing and patterning. The process is not only complicated but also wastes fabricating time and cost.
In addition, when the ILD layer 218 is formed by plasma enhanced chemical vapor deposition (PECVD), the charges in the plasma environment easily disrupt the load resistor 210b, such that the load resistor 210b cannot sustain its high resistivity, thereby affecting the reliability of the device.